FIG. 1A is the schematic circuit diagram of a stage of a conventional Dickson charge pump circuit. FIG. 1B is a cross-sectional view of a transistor M1 of the circuit depicted in FIG. 1A. FIG. 1C is a timing diagram of the circuit depicted in FIG. 1A. FIG. 1D is a schematic circuit diagram of the conventional Dickson charge pump with 8 stages implementation as depicted in FIG. 1A. Referring to FIGS. 1A, 1B, 1C and 1D, MOS transistors M3 and M4 are used to bias the body of transfer MOS M1. MG1 is the voltage level at the gate terminal of MOS device M1. CK is the clock to drive MG1 by capacitor C1. When CK is high, MG1 will be driven to higher voltage level, M1 will be turned off, and this time period is referred to as “Off Cycle”. When CK is low, MG1 will be driven to a lower voltage level, M1 will be turned on, and this time period is referred to as “On Cycle”.
The on-resistance Ron of transistors M3 and M4 is large, the body of M1 cannot properly follow the voltage toggling on source and drain of M1. In other words, the voltage change at source and drain of M1 will drive the voltage change at the body of M1. However, the voltage change response at the body of M1 is slow.
At the beginning of the “Off cycle” time t1, when VN voltage is pumped up in a short time, the body of M1 (NW1) cannot follow the voltage of VN. Before time t1, the voltage of VN is lower than the voltage of the body of M1. Starting from time t1, the voltage of VN is higher than the voltage of the body of M1 (i.e. VN>VNW1) thus the parasitic BJT on source side of M1 is turned on, leading to leakage current flowing from VN to the substrate (P-sub), which is connected to ground. This leakage current reduces efficiency of the circuit.